F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 2/09/2023

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6.1.4. Supplementary Address (Dword Offset 0xC0 – 0xC7)

A software reset has no impact on these registers. MAC supplementary addresses are not available in 10/100 and 1000 Small MAC variations.
Table 30.  Supplementary Address Registers


Name R/W Description HW Reset
0xC0 smac_0_0 RW You can specify up to four 6-byte supplementary addresses:
  • smac_0_0/1
  • smac_1_0/1
  • smac_2_0/1
  • smac_3_0/1

Map the supplementary addresses to the respective registers in the same manner as the primary MAC address. Refer to the description of mac_0 and mac_1.

The MAC function uses the supplementary addresses for the following operations:

  • to filter unicast frames when the promiscuous mode is disabled.
  • to replace the source address in transmit frames received from the user application when address insertion is enabled.

If you do not require the use of supplementary addresses, configure them to the primary address.

0xC1 smac_0_1
0xC2 smac_1_0
0xC3 smac_1_1
0xC4 smac_2_0
0xC5 smac_2_1
0xC6 smac_3_0
0xC7 smac_3_1