F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 2/09/2023

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5.2.9. PHY Power-Down

Power-down is controlled by the POWERDOWN bit in the PCS control register. When the system management agent enables power-down, the PCS function drives the powerdown signal, which can be used to control a technology specific circuit to switch off the PCS function clocks to reduce the application activity.

When the PHY is in power-down state, the PCS function is in reset and any activities on the GMII transmit and the TBI receive interfaces are ignored. The management interface remains active and responds to management transactions from the MAC layer device.

Figure 37. Power-Down