F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 2/09/2023

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7.2.7. MII Transmit

On transmit, all data transfers are synchronous to the rising edge of tx_clk. The MII data enable signal, m_tx_en, is asserted to indicate the start of a new frame and remains asserted until the last byte of the frame is present on m_tx_d[3:0] bus. Between frames, m_tx_en remains deasserted.

If a frame is received on the FIFO interface with an error (ff_tx_err asserted) the frame is subsequently transmitted with the MII error signal m_tx_err for one clock cycle at any time during the frame transfer.