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1. About the F-Tile Triple Speed Ethernet Intel FPGA IP User Guide
2. About This IP
3. Getting Started
4. Parameter Settings
5. Functional Description
6. Configuration Register Space
7. Interface Signals
8. Design Considerations
9. Timing Constraints
10. Software Programming Interface
11. Document Revision History for the F-tile Triple-Speed Ethernet Intel® FPGA IP User Guide
A. Ethernet Frame Format
B. Simulation Parameters
5.1.1. MAC Architecture
5.1.2. MAC Interfaces
5.1.3. MAC Transmit Datapath
5.1.4. MAC Receive Datapath
5.1.5. MAC Transmit and Receive Latencies
5.1.6. FIFO Buffer Thresholds
5.1.7. Congestion and Flow Control
5.1.8. Magic Packets
5.1.9. MAC Local Loopback
5.1.10. MAC Reset
5.1.11. PHY Management (MDIO)
5.1.12. Connecting MAC to External PHYs
7.1.1. 10/100/1000 Ethernet MAC Signals
7.1.2. 10/100/1000 Multiport Ethernet MAC Signals
7.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
7.1.4. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (F-Tile)
7.1.5. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS Signals
7.1.6. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals
7.1.7. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals
7.1.8. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals
7.1.9. 1000BASE-X/SGMII PCS Signals
7.1.10. 1000BASE-X/SGMII 2XTBI PCS Signals
7.1.11. 1000BASE-X/SGMII PCS and PMA Signals
7.1.1.1. Clock and Reset Signals
7.1.1.2. Clock Enabler Signals
7.1.1.3. MAC Control Interface Signals
7.1.1.4. MAC Status Signals
7.1.1.5. MAC Receive Interface Signals
7.1.1.6. MAC Transmit Interface Signals
7.1.1.7. Pause and Magic Packet Signals
7.1.1.8. MII/GMII/RGMII Signals
7.1.1.9. PHY Management Signals
7.1.1.10. ECC Status Signals
10.6.1. alt_tse_mac_get_common_speed()
10.6.2. alt_tse_mac_set_common_speed()
10.6.3. alt_tse_phy_add_profile()
10.6.4. alt_tse_system_add_sys()
10.6.5. triple_speed_ethernet_init()
10.6.6. tse_mac_close()
10.6.7. tse_mac_raw_send()
10.6.8. tse_mac_setGMII mode()
10.6.9. tse_mac_setMIImode()
10.6.10. tse_mac_SwReset()
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5.1.4.4. Frame Type Validation
The MAC function checks the length/type field to determine the frame type:
- Length/type < 0x600—the field represents the payload length of a basic Ethernet frame. The MAC function continues to check the frame and payload lengths.
- Length/type >= 0x600—the field represents the frame type.
- Length/type = 0x8100—VLAN or stacked VLAN tagged frames. The MAC function continues to check the frame and payload lengths, and asserts the following signals:
- for VLAN frames, rx_err_stat[16] in MAC variations with internal FIFO buffers or pkt_class_data[1] in MAC variations without internal FIFO buffers
- for stacked VLAN frames, rx_err_stat[17] in MAC variations with internal FIFO buffers or pkt_class_data[0] in MAC variations without internal FIFO buffers.
- Length/type = 0x8088—control frames. The next two bytes, the Opcode field, indicate the type of control frame.
- For pause frames (Opcode = 0x0001), the MAC function continues to check the frame and payload lengths. For valid pause frames, the MAC function proceeds with pause frame processing. The MAC function forwards pause frames to the user application only when the PAUSE_FWD bit in the command_config register is set to 1.
- For other types of control frames, the MAC function accepts the frames and forwards them to the user application only when the CNTL_FRM_ENA bit in the command_config register is set to 1.
- Length/type = 0x8100—VLAN or stacked VLAN tagged frames. The MAC function continues to check the frame and payload lengths, and asserts the following signals:
- For other field values, the MAC function forwards the receive frame to the user application.
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