F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 2/09/2023

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Document Table of Contents

6.3. Register Initialization

The F-tile Triple-Speed Ethernet Intel® FPGA IP supports various types of interfaces commonly used by the following Ethernet solutions:
  • 10-bit Interface
  • 1000BASE-X
  • Management Data Input/Output (MDIO) for external PHY register configuration

When using the F-tile Triple-Speed Ethernet Intel® FPGA IP with an external interface, you must understand the requirements and initialize the registers.

Register initialization mainly performed in the following configurations:

  • External PHY Initialization using MDIO (Optional)
  • PCS Configuration Register Initialization
  • MAC Configuration Register Initialization