F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 2/09/2023

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7.2.8. MII Receive

On receive, all signals are sampled on the rising edge of rx_clk. The MII data enable signal m_rx_en is asserted by the PHY to indicate the start of a new frame and remains asserted until the last byte of the frame is present on m_rx_d[3:0] bus. Between frames, m_rx_en remains deasserted.

If the PHY detects an error on the frame received from the line, the PHY asserts the MII error signal, m_rx_err, for at least one clock cycle at any time during the frame transfer.

A frame received on the MII interface with a PHY error indication is subsequently transferred on the FIFO interface with the error signal rx_err[0] asserted.