F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 2/09/2023

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Document Table of Contents

4.4. PCS/Transceiver Options

The PCS/Transceiver options are enabled only if your IP variation includes the PCS function.
Table 14.  PCS/Transceiver Options Parameters
Name Value Parameter
PCS Options
PHY ID (32 bit) Configures the PHY ID of the PCS block.
Enable SGMII bridge On/Off Turn on this option to add the SGMII clock and rate-adaptation logic to the PCS block. This option allows you to configure the PCS either in SGMII mode or 1000Base-X mode. If your application only requires 1000BASE-X PCS, turning off this option reduces resource usage.
F-tile FGT-DR Transceiver Options 4
Data clocking mode PMA/System PLL Specifies the clock to drive the datapath (core/tile/PMA Interface FIFO and RS-FEC).
Note: System PLL is required for dynamic reconfiguration.
System PLL Frequency
  • 805.664062
  • 830.078125
  • 903.125000
Specifies the frequency for System PLL.
Enable datapath Avalon Interface On/Off Enables the Avalon® memory-mapped interface datapath and exports the PDP reconfig ports.
Enable PMA Avalon Interface On/Off Enables the Avalon® memory-mapped interface to access the PMA registers and export the transceiver reconfiguration ports.

Refer to the respective device handbook for more information on dynamic reconfiguration in Intel FPGA devices.

4 Dynamic reconfiguration feature for F-tile Triple-Speed Ethernet Intel® FPGA IP is not available in the current Quartus version. These options parameters are reserved for future Quartus version.