F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 2/09/2023

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3.5. Simulating Intel® FPGA IP Cores

The Intel® Quartus® Prime software supports IP core RTL simulation in specific EDA simulators. IP generation optionally creates simulation files, including the functional simulation model, any testbench (or example design), and vendor-specific simulator setup scripts for each IP core. You can use the functional simulation model and any testbench or example design for simulation. IP generation output may also include scripts to compile and run any testbench. The scripts list all models or libraries you require to simulate your IP core.

The Intel® Quartus® Prime software provides integration with many simulators and supports multiple simulation flows, including your own scripted and custom simulation flows. Whichever flow you choose, IP core simulation involves the following steps:

  1. Generate IP HDL, testbench (or example design), and simulator setup script files.
  2. Set up your simulator environment and any simulation scripts.
  3. Compile simulation model libraries.
  4. Run your simulator.

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