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1. About this Document
2. Ashling RiscFree* IDE for Altera® FPGAs
3. Ashling Visual Studio Code Extension for Altera FPGAs
4. Ashling RiscFree* Integrated Development Environment (IDE) for Altera® FPGAs User Guide Archives
5. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Altera® FPGAs User Guide
A. Appendix
2.1. About the RiscFree* IDE for Altera® FPGAs IDE
2.2. Getting Started with the Ashling* RiscFree* IDE for Altera® FPGAs
2.3. Using Ashling* RiscFree* IDE for Altera® FPGAs with Nios® V Processor System
2.4. Using Ashling* RiscFree* IDE for Altera® FPGAs with Arm* Hard Processor System
2.5. Debugging Features with RiscFree* IDE for Altera® FPGAs
2.2.1. Installing RiscFree* IDE for Altera FPGAs
2.2.2. Getting Started with RiscFree* IDE for Altera® FPGAs
2.2.3. Creating the Project
2.2.4. Building the Application
2.2.5. Run and Debug Configurations in the RiscFree* IDE for Altera® FPGAs
2.2.6. Debug Information in the RiscFree* IDE for Altera® FPGAs
2.5.1. Debug Features in RiscFree* IDE
2.5.2. Processor System Debug
2.5.3. Heterogeneous Multicore Debug
2.5.4. Debugging µC/OS-II Application
2.5.5. Debugging FreeRTOS Application
2.5.6. Debugging Zephyr Application
2.5.7. Arm* HPS On-Chip Trace
2.5.8. Debugging the Arm* Linux Kernel
2.5.9. Debugging Target Software in an Intel® Simics Simulator Session
3.1. About the Ashling Visual Studio Code Extension
3.2. Getting Started with Ashling* Visual Studio Code Extension
3.3. Using Ashling* Visual Studio Code Extension with Nios® V Processor System
3.4. Using Ashling* Visual Studio Code Extension with Arm Hard Processor System
3.5. Debugging Features in Ashling* Visual Studio Code Extension
3.3.1. Creating Nios® V Processor BSP using Nios® V Processor BSP Generator
3.3.2. Creating Nios® V Processor Application Project using Nios® V App Generator
3.3.3. Importing Nios® V Processor Project
3.3.4. Building Nios® V Processor Project
3.3.5. Debugging a Nios® V Processor Project
3.3.6. Debugging Tools
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A.3.1. Running Ashling* GBD Server
The Ashling* GDBServer connects to the processor core with a remote GDB, which allows you to debug the software applications remotely. The Ashling* GDBServer must be ready before running the GDB.
Processor Core | Executables File |
---|---|
Nios® V Processor | <Intel Quartus Prime installation directory>/riscfree/debugger/gdbserver-riscv/ash-riscv-gdb-server.exe |
Arm* HPS core | <Intel Quartus Prime installation directory>/riscfree/debugger/gdbserver-arm/ash-arm-gdb-server.exe |
By invoking the Ashling* GDBServer with --help, you can get more information from the executables’ internal documentation about the supported GDB MONITOR commands. The table below lists the common options for starting the Ashling* GDBServer.
Options | Mandatory | Description |
---|---|---|
--device <IDCODE> | Yes | Specifies the IDCODE of the target device. Use jtagconfig to display the device IDCODE. |
--autodetect true | Yes | Enable JTAG scan chain auto-detection on the specified IDCODE. |
--probe-type usb-blaster-2 | Yes | Select Intel® FPGA Download Cable II (USB-Blaster 2) as the debug probe. |
--tap-number <number> | No | Select the TAP (test access port) with the specified IDCODE (when there is more than one TAP with the same IDCODE). |
--core-number <number> | No | Select the processor core within the same device.
|
--jtag-frequency <frequency> | No |
Specifies the JTAG frequency. The following are the valid inputs:
|
--list-probes | No | List out all the serial number for the connected debug probes. |
--instance <number> | No | Select the probe based on the serial number (persistent ID). Apply Ashling GDBServer with --list-probes to determine the serial number. |
--gdb-port <port> | No | Specifies the TCP port to connect to GDB. Default TCP at 2331. |