Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide

ID 721605
Date 4/10/2023
Document Table of Contents
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6.2. Golden Top

You can use the Golden Top project as the starting point for your designs. It comes loaded with constraints, pin locations, defined I/O standard, direction, and general termination. The DDR4 pin termination settings are not included. Refer DDR4 example designs for details.