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Ixiasoft
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information
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Ixiasoft
A.3. Clocks
Schematic Signal Name | Default Frequency |
---|---|
DDR4_HPS_REFCLKp/n | 166.6M |
DDR4_DIMM_2_REFCLKp/n | 166.6M |
Si5332_OUT2_P/N | 100M |
Si5332_OUT3_P/N | 100M |
PCIE_100M_REF_RP_AP/N | 100M |
Si5332_OUT5_P/N | 100M |
CLK_GPIO_P_4/N_4 | 100M |
Si5332_OUT7_P/N | 100M |
Si5391_A_OUT_P0A/N0A | 156.25M |
Si5391_A_OUT_P0/N0 | 156.25M |
Si5391_A_OUT_P1/N1 | 156.25M |
Si5391_A_OUT_P5/N5 | 184.32M |
Si5391_A_OUT_P6/N6 | 148.5M |
Si5391_A_OUT_P7/N7 | 368.63M |
Si5391_A_OUT_P9/N9 | 153.6M |
Si5391_B_OUT_P0/N0 | 156.25M |
CLK_13A_FGT_REFCLK4_P/N | 156.25M |
CLK_13A_FGT_REFCLK2_P/N | 184.32M |
Si5391_B_OUT_P5/N | 184.32M |
Si5391_B_OUT_P6/N6 | 148.5M |
Si5391_B_OUT_P7/N7 | 368.63M |
Si5391_B_OUT_P9/N9 | 153.6M |
CLK_13A_FGT_REFCLK3_P/N | 153.6M |
CLK_FHT_13A_P_0/N_0 | 156.25M |
CLK_FHT_13C_P_0/N_0 | 156.25M |
CLK_FGT_13C_REFCLK_2P/N | 135M |
CLK_A_12C_FGT_P_0/N_0 | 100M |
CLK_3A_GPIO_P_0/N_0 | 100M |
CLK_A_12C_FGT_P_3/N_3 | 148.5M |
CLK_3A_GPIO_P_2/N_2 | 148.5M |
CLK_A_12C_FGT_P_2/N_2 | 156.25M |
CLK_3A_GPIO_P_1/N_1 | 156.25M |
CLK_A_12C_FGT_P_4/N_4 | 156.25M |
CLK_A_12C_FGT_P_6/N_6 | 368.63M |
CLK_A_12C_FGT_P_5/N_5 | 184.32M |
CLK_B_12A_FGT_P_0/N_0 | 100M |
CLK_13A_FGT_REFCLK0_P/N | 100M |
CLK_B_12A_FGT_P_2/N_2 | 156.25M |
CLK_3C_GPIO_P_1/N_1 | 156.25M |
CLK_B_12A_FGT_P_3/N_3 | 148.5M |
CLK_3C_GPIO_P_0/N_0 | 148.5M |
CLK_B_12A_FGT_P_4 | 156.25M |
CLK_B_12A_FGT_P_5 | 184.32M |
CLK_B_12A_FGT_P_6 | 368.63M |
ToD_CLK_100M_P/N | 100M |
ETH_REFCLK_156.25M_P/N | 156.25M |
CPRI_REFCLK_153.6M_P/N | 153.6M |
CPRI_REFCLK_184.32M_P/N | 184.32M |
FMCA_REFCLK_148.5M_P/N | 148.5M |
FMCA_REFCLK_156.25M_P/N | 156.25M |
Si5391_A_156.25M_REFIN_P/N | 156.25M |
Si5391_B_156.25M_REFIN_P/N | 156.25M |
CLK_3C_GPIO_P_1/N_1 | 156.25M |
CLK_B_12A_FGT_P_3/N_3 | 148.5M |
CLK_3C_GPIO_P_0/N_0 | 148.5M |
1PPS_FPGA_CLK | 1PPS |
1PPS_SMA_OUT | 1PPS |
10MHz_SMA_OUT | 10M |
ZL_SPARE_CLK_100M | 100M |
Figure 36. Clock Tree