Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
ID
721605
Date
2/28/2025
Public
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information
A.5. Memory Interfaces
FPGA Dedicated External Memory Interface (2DPC DDR4)
Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit supports 32 GB 2DPC DDR4 with ECC support (x72). Mechanically, the development kit provides 2 dual-in memory module slots for the same. This development kit also supports 16 GB 1DPC DDR4 with ECC support (x72). Mechanically, install one RDIMM module on J5.
FPGA and HPS Shared External Memory Interface (DDR4)
DDR4 component interface is a 72 bit, single rank configuration based on x16 component. It runs at 2666 Mbps. MT40A1G16RC-062E:B from Micron is soldered down on the development kit. Both Agilex™ 7 FPGA fabric and HPS can access this external memory interface. However, they cannot be accessed at the same time.