Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide

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ID 721605
Date 11/05/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Altera® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board System MAX® 10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. BTS Test Areas 4.4. Control Onboard Clock through Clock Controller GUI 4.5. Monitor Onboard Power Regulator through Power Monitor GUI 4.6. Identify Test Pass or Fail based on BTS GUI Test Status 4.7. BTS Test Areas
4.1. Set Up BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Information Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab 4.2.5.3. The FMCB NRZ Tab 4.2.5.4. The QSFPDD800 PAM4 Tab PMA Setting 4.2.5.5. The MXPM NRZ Tab 4.2.5.6. The MXPM PAM4 Tab 4.2.5.7. The SDI NRZ Tab
5. Development Kit Hardware and Configuration x
5.1. Configuring the FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring the FPGA Device Using the AS Mode (Default Mode) 5.3. Configuring the FPGA Device Using the Avalon® -ST Mode 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card
6. Custom Projects for the Development Kit x
6.1. Adding SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards A.8. Connectors and Cables
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

4.2.5.4. The QSFPDD800 PAM4 Tab

Similar control functions with the QSFPDD NRZ tab.
Figure 19. The QSFPDD800 PAM4 Tab

PMA Setting

In addition to the PMA settings listed in the QSFPDD NRZ—PMA Setting figure, additional settings are available for the F-Tile FHT PMA. The PMA is set to the default values in the PAM4 designs.

  • Pre-emphasis tap:
    • Post-tap 2: Specifies the amount of pre-emphasis on the second post-tap of the transmitter buffer.
    • Post-tap 3: Specifies the amount of pre-emphasis on the third post-tap of the transmitter buffer.
    • Post-tap 4: Specifies the amount of pre-emphasis on the fourth post-tap of the transmitter buffer.
    • Pre-tap 3: Specifies the amount of pre-emphasis on the third pre-tap of the transmitter buffer.
Figure 20. The QSFPDD800 PAM4 Tab—PMA Setting
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