Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide

ID 721605
Date 4/10/2023
Document Table of Contents
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5.1. Configure FPGA and Access HPS Debug Access Port by JTAG

  1. JTAG access does not rely on switch S9 settings and system image.
  2. Plug the USB cable to J10 or Intel® FPGA Download Cable to J11.
  3. Open the Intel® Quartus® Prime Programmer, system console to configuration Intel Agilex® 7 FPGA SDM, system Intel® MAX® 10 and FMC JTAG nodes.
  4. Open Arm* Development Studio 5* (DS-5*) Intel SoC FPGA Edition to connect to and communicate with the HPS Debug Access Port (DAP) through the same JTAG interface.