AN 960: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Agilex® 7 E-Tile Devices

ID 709330
Date 3/27/2023
Public Procedure

  • After the FPGA is powered up and configured, the onboard oscillator provides reference clock to E-tile transceiver through refclk0.
  • Once the FPGA is up and ready, HMC7044 is configured through SPI interface.
  • refclk4 has the desired frequency as per lane rate which is sourced from HMC7044. To establish the link, refclk4 has be connected to the E-tile transceiver reference clock.
  • Once HMC7044 is locked, the E-tile transceiver reference clock is switched from refclk0 to refclk4. This clock switching process is shown in the figure below. refclk1 is an intermediate clock used during this switching process.
Figure 2. Clock Switching Steps

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