AN 960: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Agilex® 7 E-Tile Devices

ID 709330
Date 3/27/2023
Public Sync Header Alignment (SHA)

Table 1.  Sync Header Alignment Test Cases
Test Case Objective Description Passing Criteria
SHA.1 Check if Sync Header Lock is asserted after the completion of reset sequence. The following signals are read from registers:
  • CDR_Lock_XCVR_ready is read from the rx_status2 (0x88) register.
  • gear_box_status is read from the rx_status3 (0x8C) register.
  • jrx_sh_err_status is read from the rx_err_status (0x60) register.
  • CDR_Lock_XCVR_ready should be asserted to high corresponding to the number of lanes.
  • gear_box_status should be low corresponding to each lane.
  • jrx_sh_err_status should be 0. The bit fields in jrx_sh_err_status checks for sh_unlock_err, rx_gb_overflow_err, rx_gb_underflow_err, invalid_sync_header, pcfifo_empty_err, pcfifo_full_err, and cdr_locked_err.
SHA.2 Check Sync Header Lock status after sync header lock is achieved (or during the Extended Multi-Block Alignment phase) and stable. invalid_sync_header is read for Sync Header lock status from register (0x60[8]). invalid_sync_header status should be 0.

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