1.2. Hardware Setup
The JESD204C Intel® FPGA IP is instantiated in Duplex mode but only the receiver path is used. For FCLK_MULP =1, WIDTH_MULP = 4, S = 1, the core PLL generates a 187.5 MHz link clock and a 187.5 MHz frame clock. The rx_dl_signal signal is for deterministic latency measurement.
An Intel Agilex® 7 5G/Wireless Development Platform (Production Rev B Edition) is used with the ADI AD9081 AD9081-FMCA_EBZ EVM connected to the FMC+ connector of the development board. The hardware setup for ADC interoperability test is shown in the Hardware Setup figure.
- The AD9081-FMCA-EBZ EVM derives power from Intel Agilex® 7 development board through FMC+ connector.
- The E-tile transceiver reference clocks of the FPGA are supplied by Intel Agilex® 7 FPGA onboard oscillator, Silicon Labs Si5341 programmable clock generator, and HMC7044 programmable clock generator.
- The onboard oscillator provides a reference clock to the HMC7044 programmable clock generator present in the AD9081 EVM.
- The HMC7044 programmable clock generator provides the AD9081 device reference clock. The phase-locked loop (PLL) present in the AD9081 device generates the desired ADC sampling clock from the device reference clock.
- HMC7044 provides E-tile reference clock according to desired lane rate. Refer to the Clock Multiplexing section for the need and procedure to switch the E-tile reference clock.
- The JESD204C Intel® FPGA IP core PLL reference clock is supplied by the HMC7044 programmable clock generator through the FMC+ connector.
- For Subclass 1, the HMC7044 clock generator generates the SYSREF signal for the AD9081 device and for the JESD204C Intel® FPGA IP through the FMC+ connector.
- The rx_dl_signal signal is connected between the output of the FPGA and ADC 0 input of AD9081 through a single stranded wire and SMA connector arrangement to measure deterministic latency. ADC can accept voltage till 1.5 V, thus the FPGA output is connected directly to ADC0.
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