AN 960: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Agilex® 7 E-Tile Devices

ID 709330
Date 3/27/2023

1.4.1. Receiver Data Link Layer

This test area covers the test cases for sync header alignment (SHA) and extended multiblock alignment (EMBA).

On link start up, after the receiver reset, the JESD204C Intel® FPGA IP starts looking for the sync header stream that is transmitted by the device. The following registers from data link layer are read during the test, written into log files, and verified for passing criteria through TCL scripts.

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