AN 960: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Agilex® 7 E-Tile Devices

Download
ID 709330
Date 3/27/2023
Public
Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel Agilex® 7 E-Tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel Agilex® 7 E-Tile Devices x
1.1. Hardware and Software Requirements 1.2. Hardware Setup 1.3. System Description 1.4. Interoperability Methodology 1.5. JESD204C Intel® FPGA IP and ADC Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. Document Revision History for AN 960: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Agilex® 7 E-Tile Devices 1.9. Appendix
1.2. Hardware Setup x
1.2.1. Switching Reference Clocks
1.2.1. Switching Reference Clocks x
1.2.1.1. Procedure
1.4. Interoperability Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer (TL) 1.4.3. Deterministic Latency - Subclass 1 (DL)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Sync Header Alignment (SHA) 1.4.1.2. Extended Multiblock Alignment (EMBA)
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel Agilex® 7 E-Tile Devices

1.4.1.2. Extended Multiblock Alignment (EMBA)

Table 2.  Extended Multiblock Alignment Test Cases
Test Case Objective Description Passing Criteria
EMBA.1 Check if the Extended Multiblock Lock is asserted only after the assertion of Sync Header Lock. The following signals are read through registers:
  • EMB_Locked_1 is read from the rx_status5 (0x94) register.
  • EMB_Lock_err is read from the rx_err_status (0x60[19]) register.
  • The EMB_Locked_1 value should be equal to 1 corresponding to each lane. EMB_Lock_err should be 0.
EMBA.2 Check if the Extended Multiblock Lock status being stable (after extended multiblock lock or until elastic buffer is released) along with no invalid multiblock. invalid_eomb_eoemb is read from the rx_err_status (0x60[10:9]) register. invalid_eomb_eoemb should be "00".
EMBA.3 Check the lane alignment. The following values are read from registers:
  • elastic_buf_over_flow is read from the jrx_err_status (0x60) register.
  • elastic_buf_full is read from the rx_status6 (0x98) register.
  • elastic_buf_over_flow should be 0.
  • The elastic_buf_full value should be equal to 1 corresponding to each lane.
Level Two Title

Did you find the information on this page useful?

Characters remaining:

Feedback Message