AN 960: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Agilex® 7 E-Tile Devices

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ID 709330
Date 3/27/2023
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Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel Agilex® 7 E-Tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel Agilex® 7 E-Tile Devices x
1.1. Hardware and Software Requirements 1.2. Hardware Setup 1.3. System Description 1.4. Interoperability Methodology 1.5. JESD204C Intel® FPGA IP and ADC Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. Document Revision History for AN 960: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Agilex® 7 E-Tile Devices 1.9. Appendix
1.2. Hardware Setup x
1.2.1. Switching Reference Clocks
1.2.1. Switching Reference Clocks x
1.2.1.1. Procedure
1.4. Interoperability Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer (TL) 1.4.3. Deterministic Latency - Subclass 1 (DL)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Sync Header Alignment (SHA) 1.4.1.2. Extended Multiblock Alignment (EMBA)
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel Agilex® 7 E-Tile Devices

1.6. Test Results

The following table contains the possible results and their definition.

Table 6.  Results Definition
Result Definition
PASS The Device Under Test (DUT) was observed to exhibit conformant behavior.
PASS with comments The DUT was observed to exhibit conformant behavior. However, an additional explanation of the situation is included (example: due to time limitations, only a portion of the testing was performed).
FAIL The DUT was observed to exhibit non-conformant behavior.
Warning The DUT was observed to exhibit behavior that is not recommended.
Refer to comments From the observations, a valid pass or fail could not be determined. An additional explanation of the situation is included.

The following table shows the results for test cases SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, and TL.2 with different values of L, M, F, data rate, sampling clock, link clock, and SYSREF frequencies.

Table 7.  Result for Test Cases SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, and TL.2
No. L M F S HD E N NP ADC Sampling Clock (MHz) FPGA Device Clock (MHz) FPGA Frame Clock (MHz) FPGA Link Clock (MHz) Lane Rate (Gbps) Result
1 1 2 4 1 0 1 16 16 1966.08 245.76 122.88 122.88 16.22016 Pass
2 1 2 3 1 0 3 12 12 2211.84 276.48 138.24 138.24 18.24768 Pass
3 1 4 6 1 0 3 12 12 2949.12 184.32 92.16 92.16 12.16512 Pass
4 1 4 8 1 0 1 16 16 3000 375 187.5 187.5 24.75 Pass
5 1 8 12 1 0 3 12 12 1474.56 184.32 92.16 92.16 12.16512 Pass
6 1 8 16 1 0 2 16 16 2621.44 327.68 163.84 163.84 21.62688 Pass
7 1 8 24 1 0 3 16 24 1966.08 184.32 92.16 92.16 12.16512 Pass
8 2 2 2 1 0 1 16 16 1500 375 187.5 187.5 24.75 Pass
9 2 2 3 2 0 3 12 12 2621.44 245.76 122.88 122.88 16.22016 Pass
10 2 4 3 1 0 3 12 12 2949.12 184.32 92.16 92.16 12.16512 Pass
11 2 4 4 1 0 1 16 16 1474.56 184.32 92.16 92.16 12.16512 Pass
12 2 8 6 1 0 3 12 12 3000 375 187.5 187.5 24.75 Pass
13 2 8 8 1 0 1 16 16 1474.56 184.32 92.16 92.16 12.16512 Pass
14 2 8 12 1 0 3 16 24 1474.56 184.32 92.16 92.16 12.16512 Pass
15 3 6 4 1 0 1 16 16 1474.56 184.32 92.16 92.16 12.16512 Pass
16 3 12 8 1 0 1 16 16 2949.12 245.76 122.88 122.88 16.22016 Pass
17 4 2 1 1 1 1 16 16 1474.56 184.32 92.16 92.16 12.16512 Pass
18 4 2 3 4 0 3 12 12 3440.64 322.56 161.28 161.28 21.28896 Pass
19 4 4 2 1 0 1 16 16 1500 375 187.5 187.5 24.75 Pass
20 4 4 3 2 0 3 12 12 2621.44 245.76 122.88 122.88 16.22016 Pass
21 4 8 3 1 0 3 12 12 1474.56 276.48 138.24 138.24 18.24768 Pass
22 4 8 4 1 0 1 16 16 1474.56 184.32 92.16 92.16 12.16512 Pass
23 4 8 6 1 0 3 16 24 3440.64 322.56 161.28 161.28 21.28896 Pass
24 4 16 8 1 0 1 16 16 1474.56 184.32 92.16 92.16 12.16512 Pass
25 6 12 4 1 0 1 16 16 3000 375 187.5 187.5 24.75 Pass
26 8 2 1 2 1 1 16 16 2949.12 184.32 92.16 92.16 12.16512 Pass
27 8 2 3 8 0 3 12 12 3932.16 184.32 92.16 92.16 12.16512 Pass
28 8 4 1 1 0 3 16 16 3000 375 187.5 187.5 24.75 Pass
29 8 4 3 4 0 3 12 12 1966.08 184.32 92.16 92.16 12.16512 Pass
30 8 8 2 1 0 1 16 16 1474.56 184.32 92.16 92.16 12.16512 Pass
31 8 8 3 2 0 3 12 12 3932.16 245.76 122.88 122.88 16.22016 Pass
32 8 8 3 1 0 3 16 24 2211.84 276.48 138.24 138.24 18.24768 Pass
33 8 16 8 2 0 1 16 16 2211.84 184.32 92.16 92.16 12.16512 Pass
34 2 4 4 1 0 1 16 16 1966.08 245.76 61.44 61.44 8.11008 Pass
35 4 2 1 2 1 1 16 16 3932.16 245.76 61.44 61.44 8.11008 Pass

The following table shows the results for test cases DL.1, DL.2, and DL.3 with different values of L, M, F, data rate, sampling clock, link clock, and SYSREF frequencies.

Table 8.  Result for Deterministic Latency Test
No. Test L M F ADC Sampling Clock (MHz) FPGA Device Clock (MHz) FPGA Link Clock (MHz) Lane Rate (Gbps) Result JRx RBD Offset Latency (Frame Clock Cycles/Equivalent Link Clock Cycles)
1 DL.1 1 2 4 1966.08 245.76 122.88 16.22016 Pass 0 151
DL.2 1 2 4 1966.08 245.76 122.88 16.22016 Pass
DL.3 1 2 4 1966.08 245.76 122.88 16.22016 Pass
2 DL.1 1 2 3 2211.84 276.48 138.24 18.24768 Pass 0 135
DL.2 1 2 3 2211.84 276.48 138.24 18.24768 Pass
DL.3 1 2 3 2211.84 276.48 138.24 18.24768 Pass
3 DL.1 1 4 6 2949.12 184.32 92.16 12.16512 Pass 46 136
DL.2 1 4 6 2949.12 184.32 92.16 12.16512 Pass
DL.3 1 4 6 2949.12 184.32 92.16 12.16512 Pass
4 DL.1 1 4 8 3000 375 187.5 24.75 Pass 14 192
DL.2 1 4 8 3000 375 187.5 24.75 Pass
DL.3 1 4 8 3000 375 187.5 24.75 Pass
5 DL.1 1 8 12 1474.56 184.32 92.16 12.16512 Pass 0 227
DL.2 1 8 12 1474.56 184.32 92.16 12.16512 Pass
DL.3 1 8 12 1474.56 184.32 92.16 12.16512 Pass
6 DL.1 1 8 16 2621.44 327.68 163.84 21.62688 Pass 0 289
DL.2 1 8 16 2621.44 327.68 163.84 21.62688 Pass
DL.3 1 8 16 2621.44 327.68 163.84 21.62688 Pass
7 DL.1 1 8 24 1966.08 184.32 92.16 12.16512 Pass 0 366
DL.2 1 8 24 1966.08 184.32 92.16 12.16512 Pass
DL.3 1 8 24 1966.08 184.32 92.16 12.16512 Pass
8 DL.1 2 2 2 1500 375 187.5 24.75 Pass 14 85
DL.2 2 2 2 1500 375 187.5 24.75 Pass
DL.3 2 2 2 1500 375 187.5 24.75 Pass
9 DL.1 2 2 3 2621.44 245.76 122.88 16.22016 Pass 0 132
DL.2 2 2 3 2621.44 245.76 122.88 16.22016 Pass
DL.3 2 2 3 2621.44 245.76 122.88 16.22016 Pass
10 DL.1 2 4 3 2949.12 184.32 92.16 12.16512 Pass 0 112
DL.2 2 4 3 2949.12 184.32 92.16 12.16512 Pass
DL.3 2 4 3 2949.12 184.32 92.16 12.16512 Pass
11 DL.1 2 4 4 1474.56 184.32 92.16 12.16512 Pass 0 119
DL.2 2 4 4 1474.56 184.32 92.16 12.16512 Pass
DL.3 2 4 4 1474.56 184.32 92.16 12.16512 Pass
12 DL.1 2 8 6 3000 375 187.5 24.75 Pass 0 210
DL.2 2 8 6 3000 375 187.5 24.75 Pass
DL.3 2 8 6 3000 375 187.5 24.75 Pass
13 DL.1 2 8 8 1474.56 184.32 92.16 12.16512 Pass 14 156
DL.2 2 8 8 1474.56 184.32 92.16 12.16512 Pass
DL.3 2 8 8 1474.56 184.32 92.16 12.16512 Pass
14 DL.1 2 8 12 1474.56 184.32 92.16 12.16512 Pass 0 220
DL.2 2 8 12 1474.56 184.32 92.16 12.16512 Pass
DL.3 2 8 12 1474.56 184.32 92.16 12.16512 Pass
15 DL.1 3 6 4 1474.56 184.32 92.16 12.16512 Pass 0 119
DL.2 3 6 4 1474.56 184.32 92.16 12.16512 Pass
DL.3 3 6 4 1474.56 184.32 92.16 12.16512 Pass
16 DL.1 3 12 8 2949.12 245.76 122.88 16.22016 Pass 14 184
DL.2 3 12 8 2949.12 245.76 122.88 16.22016 Pass
DL.3 3 12 8 2949.12 245.76 122.88 16.22016 Pass
17 DL.1 4 2 1 1474.56 184.32 92.16 12.16512 Pass 14 78
DL.2 4 2 1 1474.56 184.32 92.16 12.16512 Pass
DL.3 4 2 1 1474.56 184.32 92.16 12.16512 Pass
18 DL.1 4 2 3 3440.64 322.56 161.28 21.28896 Pass 0 93
DL.2 4 2 3 3440.64 322.56 161.28 21.28896 Pass
DL.3 4 2 3 3440.64 322.56 161.28 21.28896 Pass
19 DL.1 4 4 2 1500 375 187.5 24.75 Pass 14 133
DL.2 4 4 2 1500 375 187.5 24.75 Pass
DL.3 4 4 2 1500 375 187.5 24.75 Pass
20 DL.1 4 4 3 2621.44 245.76 122.88 16.22016 Pass 0 132
DL.2 4 4 3 2621.44 245.76 122.88 16.22016 Pass
DL.3 4 4 3 2621.44 245.76 122.88 16.22016 Pass
21 DL.1 4 8 3 1474.56 276.48 138.24 18.24768 Pass 46 144
DL.2 4 8 3 1474.56 276.48 138.24 18.24768 Pass
DL.3 4 8 3 1474.56 276.48 138.24 18.24768 Pass
22 DL.1 4 8 4 1474.56 184.32 92.16 12.16512 Pass 0 119
DL.2 4 8 4 1474.56 184.32 92.16 12.16512 Pass
DL.3 4 8 4 1474.56 184.32 92.16 12.16512 Pass
23 DL.1 4 8 6 3440.64 322.56 161.28 21.28896 Pass 0 218
DL.2 4 8 6 3440.64 322.56 161.28 21.28896 Pass
DL.3 4 8 6 3440.64 322.56 161.28 21.28896 Pass
24 DL.1 4 16 8 1474.56 184.32 92.16 12.16512 Pass 0 157
DL.2 4 16 8 1474.56 184.32 92.16 12.16512 Pass
DL.3 4 16 8 1474.56 184.32 92.16 12.16512 Pass
25 DL.1 6 12 4 3000 375 187.5 24.75 Pass 0 155
DL.2 6 12 4 3000 375 187.5 24.75 Pass
DL.3 6 12 4 3000 375 187.5 24.75 Pass
26 DL.1 8 2 1 2949.12 184.32 92.16 12.16512 Pass 0 74
DL.2 8 2 1 2949.12 184.32 92.16 12.16512 Pass
DL.3 8 2 1 2949.12 184.32 92.16 12.16512 Pass
27 DL.1 8 2 3 3932.16 184.32 92.16 12.16512 Pass 0 91
DL.2 8 2 3 3932.16 184.32 92.16 12.16512 Pass
DL.3 8 2 3 3932.16 184.32 92.16 12.16512 Pass
28 DL.1 8 4 1 3000 375 187.5 24.75 Pass 14 114
DL.2 8 4 1 3000 375 187.5 24.75 Pass
DL.3 8 4 1 3000 375 187.5 24.75 Pass
29 DL.1 8 4 3 1966.08 184.32 92.16 12.16512 Pass 0 91
DL.2 8 4 3 1966.08 184.32 92.16 12.16512 Pass
DL.3 8 4 3 1966.08 184.32 92.16 12.16512 Pass
30 DL.1 8 8 2 1474.56 184.32 92.16 12.16512 Pass 14 91
DL.2 8 8 2 1474.56 184.32 92.16 12.16512 Pass
DL.3 8 8 2 1474.56 184.32 92.16 12.16512 Pass
31 DL.1 8 8 3 3932.16 245.76 122.88 16.22016 Pass 0 127
DL.2 8 8 3 3932.16 245.76 122.88 16.22016 Pass
DL.3 8 8 3 3932.16 245.76 122.88 16.22016 Pass
32 DL.1 8 8 3 2211.84 276.48 138.24 18.24768 Pass 0 134
DL.2 8 8 3 2211.84 276.48 138.24 18.24768 Pass
DL.3 8 8 3 2211.84 276.48 138.24 18.24768 Pass
33. DL.1 8 16 8 2211.84 184.32 92.16 12.16512 Pass 14 107
DL.2 8 16 8 2211.84 184.32 92.16 12.16512 Pass
DL.3 8 16 8 2211.84 184.32 92.16 12.16512 Pass
34 DL.1 2 4 4 1966.08 245.76 61.44 8.11008 Pass 0 120
DL.2 2 4 4 1966.08 245.76 61.44 8.11008 Pass
DL.3 2 4 4 1966.08 245.76 61.44 8.11008 Pass
35 DL.1 4 2 1 3932.16 245.76 61.44 8.11008 Pass 0 79
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