AN 960: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Agilex® 7 E-Tile Devices

ID 709330
Date 3/27/2023

1.4.3. Deterministic Latency - Subclass 1 (DL)

The Deterministic Latency Measurement Block Diagram figure shows the conceptual test setup for deterministic latency measurement. The HMC7044 is configured to provide a periodic SYSREF to both AD9081 and JESD204C Intel® FPGA IP in FPGA with the required extended multiblock period.

The deterministic latency measurement block checks the deterministic latency by measuring the number of frame clock counts between the assertion of the rx_dl_signal signal and logic OR of the MSB bit of all sample at the output of the RX JESD204C Intel® FPGA IP after the link is established or after the assertion of j204c_rx_avst_valid.

Figure 5. Deterministic Latency Measurement Block Diagram
Figure 6. Deterministic Latency Measurement Timing Diagram

With the setup in the Deterministic Latency Measurement Block Diagram figure, three test cases were defined to prove deterministic latency. The JESD204C Intel® FPGA IP does continuous SYSREF detection.

Table 4.  Deterministic Latency Test Cases
Test Case Objective Description Passing Criteria
DL.1 Check the FPGA SYSREF single detection. Check that the FPGA detects the first rising edge of SYSREF pulse.
  • Read the status of sysref_singledet (bit[2]) identifier in the rx_sysref_ctrl register at address 0x54.
  • Read the status of sysref_lemc_err (bit[0]) identifier in the rx_err register at address 0x60.
  • The value of the sysref_singledet identifier should be zero.
  • The value of sysref_lemc_err identifier should be zero.
DL.2 Check the SYSREF capture. Check that FPGA and ADC capture SYSREF correctly and restart the LEM counter. Both FPGA and ADC are also repetitively reset.
  • Read the value of rbd_count (bit[18:10]) identifier in the rx_status0 register at address 0x80.
If the SYSREF is captured correctly and the LEM counter restarts, for every reset, the rbd_count value should only drift within 1-2 link clocks to accommodate for worst-case power cycle variation.
DL.3 Check the data latency during user data phase. Check that the data latency is consistent for every FPGA and ADC reset and power cycle (using the rx_dl_signal signal as shown in the Figure 6 figure).
  • The deterministic latency measurement block in the Figure 6 figure has a counter to measure the link clock count.
The link clock count value should only drift within 1-2 link clocks for at least 10 power cycle test.

Did you find the information on this page useful?

Characters remaining:

Feedback Message