AN 960: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Agilex® 7 E-Tile Devices

ID 709330
Date 3/27/2023

1.2.1. Switching Reference Clocks

The E-tile transceiver has two fixed clock source (oscillator and Si5341) and one programmable clock source from the HMC7044 chip. To work with different lane rates programmable clock source is necessary.

The HMC7044 chip is in the AD9081 EVM and has an SPI interface to configure it. This SPI interface is controlled by the Intel Agilex® 7 FPGA. The E-tile transceiver requires a free running clock when the FPGA is configured after powered on. During initial power on configuration, the fixed clock source is used and then switched to the HMC7044 clock output, once the HMC chip is configured.

Intel recommends the source synchronous clocks for transceiver reference clock and the JESD204C dual IP IOPLL input clock. The HMC7044 chip provides flexibility to reconfigure for different lane rate. For this purpose, clock outputs from the HMC7044 chip are utilized.

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