1.3. System Description
The following system-level diagram shows how the different modules are connected in this design.
In this setup, for example L = 6, M = 12, and F = 4, the data rate of transceiver lanes is 24.75 Gbps.
The Si5341 OUT4 generates 100 MHz clock to mgmt_clk. The E-tile transceiver reference clock is subjected to multiplexing and is done with 3 clock sources. The first clock is the refclk_xcvr signal, which is supplied from the FPGA onboard oscillator and has the frequency of 156.25 MHz. The second clock is the refclk_xcvr1 signal, which is supplied from Si5341 OUT1 clock generator and has the frequency of 156.25 MHz.
The Si5341 out4 generates 100 MHz clock to mgmt_clk. The E-tile transceiver has 3 clock sources—LMK onboard oscillator (156.25 MHz), Si5341 OUT0 (156.25 MHz), and HMC7044 OUT8. The HMC7044 generates the transceiver reference clock frequency of 375 MHz. This clock is refclk_xcvr4, which is Lane Rate*1000/66 in its frequency. Refer to the Clock Multiplexing section for the need and procedure for switching clocks.
The HMC7044 also generates 187.5 MHz for the JESD204C Intel® FPGA IP's core PLL reference clock and a periodic SYSREF signal of 11.71875 MHz through the FMC connector.
The JESD204C Intel® FPGA IP is instantiated in Duplex mode but only the receiver path is used. For FCLK_MULP =1, WIDTH_MULP = 4, and S = 1, the core PLL generates a 187.5 MHz link clock and a 187.5 MHz frame clock. The rx_dl_signal signal is for deterministic latency measurement.
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