PCB Stackup Design Considerations for Intel® FPGAs

ID 683883
Date 6/28/2017
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Document Table of Contents
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1.7.2.3. Stratix® V Transceiver Channel Breakout Recommendations

For Stratix® V GX, GT, and GS devices, some transceiver TX channel pins are located near regular I/O pins
Figure 17.  Stratix® V I/O Adjacent to TX Pins
For these pins, crosstalk coupling from the I/O pins to the TX pins can degrade the TX channel performance. To minimize the coupling, do the following:
  • If possible, avoid using those I/O pins and assign them as outputs driving ground in the Stratix® V software.
  • If it is necessary to use those I/Os pins near the TX pins, assign lower voltage swing I/Os to those pins and avoid using 3.0 V or 2.5 V I/O standards. The following I/O standards are preferred for use on those I/O pins:
    • LVDS
    • SSTL or HSTL (1.2 V, 1.5 V, or 1.8 V)
    • 1.2 V non-voltage referenced I/O standard
    • 1.5 V non-voltage referenced I/O standard
    • 1.8 V non-voltage referenced I/O standard
  • Choose lower current drive strength whenever possible.
  • Assign low voltage I/O functions that switch less frequently.
  • Apply internal terminations where possible to reduce overshoot and ringing.
  • Limit the inductive coupling region between the I/O and TX pins. You can do this by limiting the depth of the I/O signal breakout to specific routing layers. Intel® FPGA recommends limiting those I/O breakouts to a depth of 40 mils or less to reduce the mutual inductive coupling region of the I/O and TX breakout via.
Figure 18. Limiting Mutual Inductive Coupling