PCB Stackup Design Considerations for Intel® FPGAs

ID 683883
Date 6/28/2017
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1.4.4. Power and Ground Layers

Power and ground layers are determined by the number of different power rails that require a separate layer on the board, the reference and return path requirements, and any isolation requirements. Power is typically shared as much as possible on any designated power layer to reduce the total layer count. As a result, power layers tend to be segmented and ground layers are solid planes that fill the entire layer. Also, power is typically placed next to a ground layer to create planar capacitance, which aids high-frequency decoupling, reduces electromagnetic interference (EMI) radiation, and enhances electromagnetic compliance (EMC) robustness.

You can generally use both power and ground layers for impedance reference and current return paths for signal layers. However, given a choice between using a power or ground plane as the signal reference or return path, always choose the ground plane. In addition to the likelihood of the power plane for FPGA designs being segmented, using the power plane as the return path for high-speed routing layers allows switching noise to couple to the power plane. Avoid this situation especially for sensitive power rails, such as transceiver analog and PLL power where any additional noise on those rails can directly impact device performance. One way to avoid this situation is to design the stackup topology so that the split power planes are completely isolated from the signal layers by sandwiching the segmented power layers between solid ground layers. Below figure (left) shows an example of two segmented power planes (PWR1 and PWR2) that are completely isolated between two solid ground planes. Although this topology requires more ground layers, it is preferred over the power-ground-power construction shown in below figure (right) because it removes the concern of having to manage signals crossing split power planes during layout.

Figure 10. Split Power Plane Topologies