1.7.1. Stratix® 10 Device Recommendations 1.7.2. Stratix® V Device Recommendations 1.7.3. Stratix IV Device Recommendations 1.7.4. Arria® 10 Device Recommendations 1.7.5. Arria® V Device Recommendations 1.7.6. Arria II Device Recommendations 1.7.7. Cyclone® 10 Device Recommendations 1.7.8. Cyclone® V Device Recommendations 1.7.9. Cyclone® IV Device Recommendations 1.7.10. Cyclone III Device Recommendations
22.214.171.124. Rules for Transceiver Power Plane Placement
Follow these rules for placing the transceiver power plane in an Intel® device:
- The sensitive transceiver power rails are most susceptible to noise and can directly impact channel jitter performance. As a result, the transceiver power rails usually have the highest priority in the power plane stackup placement over other power rails unless either of the following conditions apply:
- The transceiver rails have internal regulation that helps isolate them from on-board noise. Internally regulated power rails can be placed further away from the FPGA device.
- The current demand of the transceiver power rail is low enough to yield a high impedance target that is easily decoupled even when their power planes are placed further away from the FPGA device.
- Place critical transceiver power rails closest to the FPGA device to minimize the BGA via inductance. For example, critical power rails in a Stratix® V transceiver device include the VCCR (transceiver receive path power) and VCCT (transceiver transmit path power) power rails.
Figure 12. Transceiver Power Plane Placement Close to an FPGA Device