PCB Stackup Design Considerations for Intel® FPGAs

ID 683883
Date 6/28/2017
Public
Document Table of Contents

1.4.7. Plane Layer Separation

To benefit from the inherent planar capacitance associated with the different potential planes, make the power-to-ground layer separation as small as possible. Because the dielectric breakdown voltage (DBV) in all common PCB materials is generally 1000 V/mil or higher, dielectric failure between power and ground planes is not a concern for typical electronic applications where the voltage requirement is usually 12 V and lower. As a result, when designing planar capacitance, use the thinnest core dielectric available for the power-ground sandwich for the highest capacitance per planar area.

The thinnest standard core dielectric commonly used for the power-ground planar capacitance without incurring a cost premium is typically 3 mils. For thinner cores, several manufacturers offer 2 mil core, 1 mil core, and even sub-1 mil core thicknesses at an additional cost. Consider the ZBC cores from vendors like Sanmina, FaradFlex cores from Oak Mitsui Technologies, or ECM (Embedded Capacitance Material) cores from 3M Corporation for constructing even larger buried capacitances per area within the PCB stackup.