PCB Stackup Design Considerations for Intel® FPGAs

ID 683883
Date 6/28/2017
Public
Document Table of Contents
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1.4.5.1. General Rules for Capacitor and Power Plane Placement

Follow these rules for placing the capacitor and power plane in an Intel® device:
  • Place each decoupling capacitor in close proximity to the corresponding power plane it decouples, so the capacitor mounting inductance loop is minimized .
  • If possible, place the power and ground planes in close proximity to the FPGA device so they minimize the BGA via inductance loop.
Figure 11. Capacitor and Power Plane Placement to Minimize Mounting Iductance