PCB Stackup Design Considerations for Intel® FPGAs

ID 683883
Date 6/28/2017
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1.4.3. High Speed Signal Layer Planning

When routing high-speed traces such as FPGA transceiver signal pairs, plan the routing layer during the stackup design. For devices with a limited number of transceiver channels, it may be easier to strategically assign just a few signal layers for all the channel routes, so the stubs of the through-vias are minimized and the added cost of backdrilling is eliminated.

Figure 7. Through-Via with Minimal Short Stub

However, for high channel count FPGAs such as the Stratix® V device family, the increased channel density requires more than a few layers to accommodate all the channel routing. This means that not all channel via stubs can be optimized out by layer assignment. For these cases, backdrilled or blind vias must be used for the best signal integrity performance of the channel.

Figure 8. Backdrilled (left) and Blind Via (right)

Another consideration for transceiver signal layer assignment results from the physical nature of press-fit connectors, as most of the backplane connectors consider the penetration depth of the signal pins. This depth limits the extent of backdrilling because the penetration of the connector pins determines the maximum backdrilled depth. Therefore, for signals that route to press-fit backplane connectors, assign the signal layer equal to or below the penetration depth of the connector pins to allow backdrilling to be fully effective. For example, routing transceiver channels on layers above the penetration depth of the backplane connector results in the connector pins acting as a stub, even when backdrilling is applied.

Figure 9. Maximum Backdrilled Depth of the Connector Pins