PCB Stackup Design Considerations for Intel® FPGAs

ID 683883
Date 6/28/2017
Document Table of Contents Rules for High-Current Power Rails

Follow these rules for placing the high-current power rails in an Intel® device:
  • High-current power rails result in lower target impedance and present a greater challenge for decoupling. As a general rule, high-current power rails should typically be placed close to the FPGA device to minimize the BGA via inductance. However, depending on whether non-transceiver or transceiver-based devices are used, the priority can be adjusted to optimize the high-current power rail placement:
    • For non-transceiver devices (such as Stratix® V E devices), high-current rails such as core power (VCC) should be placed closest to the FPGA device because there are no sensitive transceiver power rails requiring a higher priority.
      Figure 13. Placement of Core Power in Non-Transceiver Devices
    • For transceiver-based devices (such as Stratix® V GX, GT, or GS devices), high-current rails should receive second priority behind the critical transceiver powers. As second priority, these rails are usually placed on the next available power layer after the critical transceiver power. However, for high-current core power, place the rails furthest from the FPGA device to minimize the capacitor mounting inductance while benefiting from the reduced effective BGA via inductance that result from having an increased number of parallel core power and ground via pairs. Do not share power or ground vias in the BGA breakout, because this negates the benefits of having parallel power and ground vias to reduce the effective BGA via inductance. Furthermore, because some device packages incorporate On-Package-Decoupling (OPD) for core power, placing core power furthest from the FPGA device provides greater flexibility for placement of other high-current rails within the stackup.
Figure 14. Placement of High-Current Rails for Transceiver-Based Devices