PCB Stackup Design Considerations for Intel® FPGAs

ID 683883
Date 6/28/2017
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Document Table of Contents
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1.4.5. Power Plane and Capacitor Placement Strategy

This section provides specific recommendations for setting the power plane priorities within the PCB stackup and the placement of decoupling capacitors relative to those power planes in Intel® devices. The method used to determine the power plane and capacitor placement priority is mainly determined by the Frequency Domain Target Impedance Method (FDTIM).

In general, the rules for capacitor and power plane placement depend on the resulting target impedance of the power rail and the goal of minimizing the various inductances to best meet those target impedances. Placement of power planes and their associated decoupling capacitors in non-optimal locations within the PCB stackup can limit their effectiveness in delivering power, resulting in higher than desired jitter.