Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 7/14/2023

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3.4.2. MSI Interrupt Controller

The MSI Interrupt controller receives the necessary MSI information such as the message address and data from the PCIe Hard IP configuration output interface (tl_cfg_*). The MSI Interrupt controller uses this information to create Memory Write transaction. The MSI Interrupt controller has the necessary storage to hold the MSI addr/data for that specific function and user vector number.

The MSI Interrupt controller also gets the MSI Mask bits from the tl_cfg interface. If the MSI is masked for a specific function, the MSI Interrupt controller does not send the MSI for that function. In addition, it provides the Hard IP information on MSI Pending bits.

When the user requests the generation of the MSI, the user provides MSI vector (number) and user function information which the MSI Interrupt Controller indexes to get the MSI addr/data and send this information to the BAS. The MSI capability message control register [6:4] selects the number of the MSI vectors per function. The MSI vector input (msi_num_i[4:0]) are used to manipulate the MSI data LSB bits as per the PCIe specification.

The BAS logic takes the MSI request from the MSI Interrupt controller and forms a Memory Write TLP. The internal request to Interrupt Gen is MSI_Pending & ~MSI_Mask. The MSI pending is User_MSI & MSI_En (from Hard IP).

Figure 10. MSI Controller
Figure 11. MSI Request Timing Diagram
Figure 12. MSI Memory Write Transaction

The BAS logic Arbs for the Interrupt ping (on the Side band wires) from the Interrupt controller and sends the MSI on the AVST interface to the scheduler.

For MSI Request Interface signals, refer to MSI Interface