Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 7/14/2023
Public

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Document Table of Contents

2.1.2. Root Port Mode

  • MCDMA H-Tile: PCIe Gen3 x16/x8 in Intel® Stratix® 10 GX and Intel® Stratix® 10 MX devices
  • MCDMA P-Tile: PCIe Gen4/Gen3 x16 and 4x4 ports in Intel® Stratix® 10 DX and Intel Agilex® 7 devices
  • MCDMA F-Tile: PCIe Gen4/Gen3 x16/x8, 1x8, 2x4 and 4x4 in Intel Agilex® 7 device
  • MCDMA R-Tile:
    • PCIe Gen5/Gen4/Gen3 2x8 ports in Intel Agilex® 7 devices.
    • PCIe Gen4/Gen3 x16 and 4x4 ports only in Intel Agilex® 7 I-Series FPGA Development Kit DK-DEV-AGI027R1BES R-Tile B0 revision.
  • Configuration Slave (CS) interface for accessing Endpoint’s config space
  • Address Translation Table (ATT) is supported in BAS mode. MCDMA H-Tile IP does not support ATT.
  • User mode options:
    • Bursting Avalon Master (BAM)
    • Bursting Avalon Slave (BAS)
    • BAM and BAS
  • Maximum payload size supported:
    • Intel® Stratix® 10 GX and Intel® Stratix® 10 MX devices: 512 bytes
    • Intel® Stratix® 10 DX and Intel Agilex® 7 devices: 512 / 256 / 128 bytes