Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 7/14/2023
Public

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4.3. Resets

Table 36.  Multi Channel DMA IP for PCI Express Reset Signals
Signal Name I/O Type Description
H-Tile
pin_perst_n Input This is an active-low input to the PCIe Hard IP, and implements the PERST# function defined by the PCIe specification.
npor Input Application drives this active-low reset input to the PCIe Hard IP. This resets entire PCIe Hard IP. If not used, you must tie this input to 1.
app_nreset_status Output

This is an active low reset status. This is deasserted after the PCIe Hard IP has come out of reset.

ninit_done Input

This is an active low input signal. A "1" indicates that the FPGA device is not yet fully configured.

A "0" indicates the device has been configured and is in normal operating mode.

To use the ninit_done input, instantiate the Reset Release Intel FPGA IP in your design and use its ninit_done output. The Reset Release IP is required in Intel Stratix 10 design. It holds the Multi Channel DMA for PCI Express IP in reset until the FPGA is fully configured and has entered user mode.

P-Tile and F-Tile and R-Tile
pin_perst_n Input See H-Tile pin_perst description
ninit_done Input See H-Tile ninit_done description
app_rst_n Output

Resets MCDMA soft IP blocks and user logic. app_rst_n is asserted when software writes to SW_RESET register bit[0].

p0_pld_link_req_rst_o Output Warm reset request to application
p0_pld_warm_rst_rdy_i Input Warm reset ready from application
i_gpio_perst#_n Input

This is an active-low reset to each port when Enable Independent Perst option is enabled.

Note: This signal is only enable for F-Tile.
app_slow_reset_status_n Output

This is the equivalent signal for app_rst_n in the slow_clk domain.

Note: This signal is only enabled for R-Tile.
cold_perst_n_i Input

When enabled, these active-low signals independently trigger cold resets to individual PCIe Controllers. If these inputs are not used, they should be tied off to 1.

warm_perst_n_i Input

When enabled, these active-low signals independently trigger cold resets to individual PCIe Controllers. If these inputs are not used, they should be tied off to 1.

p0_ip_rst_n_o Output

These active-low output signals are exposed to the application logic and indicate the status of the Hard Reset Controller triggering resets to individual PCIe Controllers.

Note: This signal is only enabled for R-Tile.