Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 7/14/2023

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4.4.3. Avalon-MM Read Master (D2H)

The D2H Avalon-MM Read Master interface is use to read D2H DMA data from the external AVMM slave. This port is 128-bit (x4) / 256-bit (x8/x4*) / 512-bit (x16) read master that is capable of reading maximum 512 bytes of data per AVMM transaction.

Note: In R-Tile, the Port x4 can be 256 bit write master when Gen4 4x4 Interface - 256 bit is selected in PCI Express Hard IP Mode.
Table 39.  Avalon-MM Read Master (D2H)

Interface Clock Domain for H-Tile: coreclkout_hip

Interface Clock Domain for P-Tile, F-Tile and R-Tile: app_clk

Signal Name I/O Type Description
d2hdm_read_o Output D2H Read.
d2hdm_address_o[63:0] Output D2H Read Write Address.

x16: d2hdm_byteenable_o[63:0]

x8/x4*: d2hdm_byteenable_o[31:0]

x4 (128-bit): d2hdm_byteenable_o[15:0]

Output D2H Byte Enable

x16: d2hdm_burstcount_o[3:0]

x8/x4*: d2hdm_burstcount_o[4:0]

x4 (128-bit): d2hdm_burstcount_o[5:0]

Output D2H Burst Count.
d2hdm_waitrequest_i Input D2H Write WaitRequest.
d2hdm_readdatavalid_i Input D2H Read Data Valid.

x16: d2hdm_readdata_i[511:0]

x8/x4*: d2hdm_readdata_i[255:0]

x4 (128-bit): d2hdm_readdata_i[127:0]

Input D2H Read Data.
d2hdm_response_i[1:0] Input Tied to 0