Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 7/14/2023

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4.4.2. Avalon-MM Write Master (H2D)

The H2D Avalon-MM Write Master interface is used to write H2D DMA data to the external Avalon-MM slave. This port is 128-bit (x4) / 256-bit (x8/x4*)/ 512-bit (x16) write master that is capable of writing maximum 512 bytes of data per AVMM transaction. The WaitRequestAllowance of this port is enabled allowing the master to transfer continuously N data phases after the WaitRequest signal has been asserted.

Value of <N> for H2D AVMM Master is as follows:
  • 512-bit data-width is 16
  • 256-bit data-width is 32
  • 128-bit data-width is 64
Note: In R-Tile, the Port x4 can be 256 bit write master when Gen4 4x4 Interface - 256 bit is selected in PCI Express Hard IP Mode.
Table 38.  Avalon-MM Write Master (H2D)

Interface Clock Domain for H-Tile: coreclkout_hip

Interface Clock Domain for P-Tile, F-Tile and R-Tile: app_clk

Signal Name I/O Type Description
h2ddm_waitrequest_i Input H2D Wait Request
h2ddm_write_o Output H2D Write
h2ddm_address_o[63:0] Output H2D Write Address

x16: h2ddm_burstcount_o[3:0]

x8/x4*: h2ddm_burstcount_o[4:0]

x4 (128-bit): h2ddm_burstcount_o[5:0]

Output H2D Write Burst Count

x16: h2ddm_writedata_o[511:0]

x8/x4*: h2ddm_writedata_o[255:0]

x4 (128-bit): h2ddm_writedata_o[127:0]

Output H2D Write Data Payload

x16: h2ddm_byteenable_o[63:0]

x8/x4*: h2ddm_byteenable_o[31:0]

x4 (128-bit): h2ddm_byteenable_o[15:0]

Output H2D Byte Enable