Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 7/14/2023

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3.5.2. 14 bit AVMM address format

Config Slave supports 14-bit address format starting with Intel Quartus Prime Pro Edition v21.3. In this format, the AVMM slave address width is limited to 14 bits as shown in the figure below.

Note: Support for 29-bit address format is not available in Intel® Quartus® Prime Pro Edition v21.3 onwards.
Figure 15. 14 bit Address Format

The two most significant bits [13:12] determines whether address [11:0] is used to form a Config TLP sent downstream or used to write to/read from local Config Slave registers.

Table 24.  Address Bits [13:12] Definition
Bits [13:12] Description
2’b00 Config TLP Type 0
2’b01 Config TLP Type 1
2’b10 Local CS address space 14’h2000 – 14’h2FFF (BDF register, etc)
2’b11 Local CS address space 14’h3000 – 14’h3FFF (ATT tables)

The following is a list of local CS registers that are supported in 14-bit address mode.

Table 25.  Local CS Registers supported in 14 bit address mode
Local CS Address Offset Name Access Comment
14’h2000 Scratch Pad Register RW
14’h2004 BDF Register RW {Bus[7:0], Device[4:0], Function[2:0]}
14’h3000 – 14’h3FFF ATT for BAS RW Address range for Address Translation Table
Note: Refer to Root Port Address Translation Table Enablement for information on an ATT programming example.