Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 7/14/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.10.3. Application Specific Bits

Table 34.  Application Specific Bits
Bit [2] Bit [1] Bit [0] Description
0 1 1

Reserved

0 1 0

Reserved

0 0 1

Data mover considers this as WB and picks the address/data from AVST sink interface in D2H direction (d2hdm_desc).

Not applicable for H2D, and external DMA controller must drive 0.

0 0 0

Reserved