Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 7/14/2023
Public

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Document Table of Contents

6.4. Example Designs

Figure 37. Example Design Settings [for x16 mode]
Figure 38. Example Design Settings [for 2x8 mode]
Table 89.  Example Designs
Parameter Value Default Value Description

Simulation

On / Off

True

When Simulation box is checked, all necessary filesets required for simulation are generated. When this box is NOT checked, filesets required for Simulation are NOT generated. Instead a Platform Designer example design system is generated.

Note: Multiple physical functions and SR-IOV are not supported for simulation. When you generate an example design, turn off Simulation.

Synthesis

On / Off

True

When Synthesis box is checked, all necessary filesets required for synthesis are generated. When Synthesis box is NOT checked, filesets required for Synthesis are NOT generated. Instead a Platform Designer example design system is generated

Generated file format

Verilog

Verilog

HDL format

Current development kit

None

MCDMA P-Tile IP:
  • Agilex 7 F-Series P-Tile ES0 FPGA Development Kit
  • Agilex 7 F-Series P-Tile Production FPGA Development Kit
  • Stratix 10 DX P-Tile Production FPGA Development Kit
MCDMA F-Tile IP:
  • None
  • Intel Agilex 7 F-Series F-Tile FPGA Devkit DK-DEV-AGF027FES
  • Intel Agilex 7 F-Series F-Tile FPGA Devkit DK-DEV-AGF027F1ES
MCDMA R-Tile IP:
  • None
  • Intel Agilex 7 I-Series FPGA DevKit DK-DEV-AGI027RES
  • Intel Agilex 7 I-Series FPGA DevKit DK-DEV-AGI027R1BES
 

This option provides supports for various Development Kits listed. The details of Intel FPGA Development kits can be found on Intel FPGA website.

If this menu is grayed out, it is because no board is supported for the options selected (for example, synthesis deselected).

If an Intel FPGA Development board is selected, the Target Device used for generation is the one that matches the device on the Development Kit

Currently Selected Example Design

PIO using MQDMA Bypass mode

Device-side Packet Loopback

Packet Generate/Check

AVMM DMA

Traffic Generator/Checker

External Descriptor Controller

 

Based on MCDMA setting for "User Mode" and "Interface Type" different Example Designs are supported.

List of Example design options are:

User Mode=MCDMA, BAM+MCDMA and BAM+BAS+MCDMA* Interface Type=AVST:
  • PIO using MQDMA Bypass mode
  • Device-side Packet Loopback
  • Packet Generate/Check
User Mode=MCDMA, BAM+MCDMA and BAM+BAS+MCDMA*, Interface Type=AVMM:
  • PIO using MQDMA Bypass mode
  • AVMM DMA
User Mode=Bursting Master:
  • PIO using MQDMA Bypass mode
User Mode=BAM+BAS:
  • PIO using MQDMA Bypass mode
  • Traffic Generator/Checker
User Mode=Data Mover Only:
  • PIO using MQDMA Bypass mode
  • External descriptor controller
Note: For more information about example designs, refer to the Multi Channel DMA Intel FPGA IP for PCI Express Design Example User Guide.