Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 7/14/2023

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Document Table of Contents

1.2. Known Issues

The following summarizes known issues in the current IP release:
  1. Multichannel D2H AVST configuration has stability issues when total number of D2H channels configured is greater than 256
  2. Design Example simulation in Intel® Quartus® Prime 23.2 release is failing for BAM+BAS+MCDMA user mode in H-Tile, when SRIOV is enabled.
  3. MCDMA R-Tile Design Example simulations are not supported in Intel® Quartus® Prime 23.2 release, except for PIO using MCDMA Bypass Mode Design Example. Simulations only supported in VCS* / VCS* MX simulators.
  4. In Ubuntu 22.04 LTS Operating System, MCDMA custom driver gets stuck failing Tx & Rx queues when Virtual Function I/O (VFIO) kernel module and MSIX mode are set.
  5. Avalon-ST Source (H2D) interface data can get corrupted, if a Completion timeout event occurs for H2DDM descriptor fetch. This issue happens only if the SOP descriptor is fetched successfully and the EOP descriptor for a channel got missed because of the Completion timeout event.
  6. FLR request is not completed gracefully, when assertion of Soft reset happens during FLR request is still under process.
  7. MCDMA Root Port may drop multi-function Mem Rd Packets targeted to remote device as multi- function enabled End Point.
  8. BAM + BAS PIO test does not consistently pass when DPDK driver is testing BAM only and SRIOV is enabled.
  9. netdev_app tool used with Network Device Driver does not work with PIO bypass test.
Note: These issues may be addressed in a future release of Intel® Quartus® Prime software.