3.2.2. Example Link Bring Up using F-Tile Ethernet Intel® FPGA Hard IP
This section covers an example of link bring up using the Quartus-generated F-tile Ethernet IP design example. After you compile the F-tile Ethernet IP core design example and configure the appropriate device, you can use the System Console to program the IP core. Perform the following steps to establish the Ethernet link:
If you configure your IP in external loopback or connected to link partner:
- In the Intel® Quartus® Prime Pro Edition software, go to Tools > In-System Sources and Probes Editor window to assert and de-assert all resets. For more information, refer to F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide.
- Once the reset is initiated, navigate to Tools > System Debugging Tools > System Console window and load your .sof design.
- Under Statistics Counter tab, navigate to the Transmitter and Receiver Statistics.
- Click Start Reading All Status.
- Click Reset Receiver/Transmitter Statistics.
- Click Start Packet Generator in Statistics Counter tab and click Start Reading Receiver/Transmitter Statistics.
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