Ethernet Toolkit User Guide

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ID 683793
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Ethernet Toolkit Overview 2. Setting up the Ethernet Toolkit 3. Functional Description 4. Document Revision History for the Ethernet Toolkit User Guide
1. Ethernet Toolkit Overview x
1.1. Features 1.2. Supported Ethernet IP Cores and Devices
2. Setting up the Ethernet Toolkit x
2.1. System Requirements and Prerequisites 2.2. Running the Ethernet Toolkit
2.1. System Requirements and Prerequisites x
2.1.1. System Requirements 2.1.2. Enabling your Design for the Ethernet Toolkit
3. Functional Description x
3.1. Ethernet Toolkit Groups and Tabs 3.2. Link Bring Up Guidelines 3.3. Ethernet Toolkit Multirate Support 3.4. Ethernet Toolkit Subsystem Support 3.5. Ethernet Toolkit GTS Ethernet Hard IP Support
3.1. Ethernet Toolkit Groups and Tabs x
3.1.1. IP Configuration and Other Information 3.1.2. General Commands 3.1.3. Settings 3.1.4. Status 3.1.5. Statistics Counters 3.1.6. Testing Features
3.1.2. General Commands x
3.1.2.1. Loopback 3.1.2.2. Resets
3.1.4. Status x
3.1.4.1. Link Bring Up 3.1.4.2. PCS Status 3.1.4.3. PHY Status 3.1.4.4. MAC Settings 3.1.4.5. AN and LT Status
3.1.5. Statistics Counters x
3.1.5.1. Example Design Packet Generator Settings 3.1.5.2. Transmitter and Receiver Statistics 3.1.5.3. RS-FEC
3.1.5.1. Example Design Packet Generator Settings x
3.1.5.1.1. Packet Generator for E-, H-, and L-Tile Ethernet IPs 3.1.5.1.2. Packet Generator for F-Tile Ethernet IP
3.1.5.2. Transmitter and Receiver Statistics x
3.1.5.2.1. Effective Bandwidth Calculation
3.1.5.3. RS-FEC x
3.1.5.3.1. 32-Bit Soft CWBIN Counter Status
3.1.6. Testing Features x
3.1.6.1. Example Design PHY and Packet Generator Loopback Test 3.1.6.2. Read Register 3.1.6.3. Write to Register
3.2. Link Bring Up Guidelines x
3.2.1. Example Link Bring Up Using E-Tile Hard IP 3.2.2. Example Link Bring Up Using F-Tile Hard IP 3.2.3. Example Link Bring Up Using GTS Ethernet Hard IP
1. Ethernet Toolkit Overview
2. Setting up the Ethernet Toolkit
3. Functional Description
4. Document Revision History for the Ethernet Toolkit User Guide

3.2.2. Example Link Bring Up using F-Tile Ethernet Intel® FPGA Hard IP

This section covers an example of link bring up using the Quartus-generated F-tile Ethernet IP design example. After you compile the F-tile Ethernet IP core design example and configure the appropriate device, you can use the System Console to program the IP core. Perform the following steps to establish the Ethernet link:
If you configure your IP in external loopback or connected to link partner:
  1. In the Intel® Quartus® Prime Pro Edition software, go to Tools > In-System Sources and Probes Editor window to assert and de-assert all resets. For more information, refer to F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide.
  2. Once the reset is initiated, navigate to Tools > System Debugging Tools > System Console window and load your .sof design.
  3. Under Statistics Counter tab, navigate to the Transmitter and Receiver Statistics.
  4. Click Start Reading All Status.
  5. Click Reset Receiver/Transmitter Statistics.
  6. Click Start Packet Generator in Statistics Counter tab and click Start Reading Receiver/Transmitter Statistics.
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