Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide

ID 683788
Date 10/08/2019
Public
Document Table of Contents

2.7. Guaranteeing Timing Closure in the Intel Arria 10 SoC Custom Platform

When modifying the Intel Arria 10 SoC Development Kit Reference Platform into your own Custom Platform, ensure that guaranteed timing closure holds true for your Custom Platform.
  1. Establish the floorplan of your design.
    Important: Consider all design criteria outlined in the FPGA System Design section of the Intel® FPGA SDK for OpenCL™ Custom Platform Toolkit User Guide.
  2. Ensure that the AOCL_BOARD_PACKAGE_ROOT environment variable points to your Custom Platform.
  3. Compile several seeds of the INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest/boardtest.cl file until you generate a design that closes timing cleanly.
    To specify the seed number, include the -seed=<N> option in your aoc command.
  4. Copy the base.qar file from the INTELFPGAOCLSDKROOT/board/a10soc/ directory into your Custom Platform.
  5. Use the flat.qsf file in the a10soc Reference Platform as references to determine the type of information you must include in the flat.qsf file for your Custom Platform.
    The base.qsf and top.qsf files automatically inherit all the settings in the flat.qsf file. However, if you need to modify Logic Lock Plus region or PR assignments, only make these changes in the base.qsf file.
  6. Ensure that the environment variable CL_CONTEXT_COMPILER_MODE_INTELFPGA=3 is not set.
  7. Run the boardtest_host executable.

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