1.4. Contents of the Intel Arria 10 SoC Development Kit Reference Platform
|File or Directory||Description|
|board_env.xml||An XML file that describes the Reference Platform to the Intel® FPGA SDK for OpenCL™ .|
|hardware||Contains the Intel® Quartus® Prime project templates for the two board variants. Each a10soc Reference Platform board variant implements the entire OpenCL hardware system on a given Intel Arria 10 SoC Development Kit.
See Table 2 for a list of files in this directory.
|arm32||Directory that contains the following:
|acl_kernel_interface_soc_pr.qsys||Platform Designer system that implements interface to kernel system in board system.|
|base.qsf|| Intel® Quartus® Prime Settings File for the base project revision.
To compile to base revision, add the -bsp-flow=base argument to aoc command (for example, aoc -bsp-flow=base myKernel.cl).
Use this revision when porting the a10soc Reference Platform to your own Custom Platform. The Intel® Quartus® Prime Pro Edition software compiles this base project revision from source code.
|base.qar|| Intel® Quartus® Prime Archive File containing base.qdb, pr_base.id, and base.sdc. This file is generated by the scripts/post_flow_pr.tcl file during base revision compile, and is used during import revision compilation.
|board.qsys||Platform Designer system that implements the board interfaces (that is, the static region) of the OpenCL hardware system.|
|board_spec.xml||XML file that provides the definition of the board hardware interfaces to the SDK.|
|DMA_system.qsys||Platform Designer system that implements DMA between HPS memory and FPGA memory in the a10soc_2ddr board variant|
|dual_port_splitter.qsys||Platform Designer system that splits requests on single slave to two channels. Used for utilizing two FPGA2SDRAM ports on HPS.|
Intel® Quartus® Prime Settings File for the flat project revision. This file includes all the common settings, such as pin location assignments, that are used in the other revisions of the project (that is, base and top). The base.qsf and top.qsf files include, by reference, all the settings in the flat.qsf file. The Intel® Quartus® Prime software compiles the flat revision with minimal location constraints. The flat revision compilation does not generate a base.qar file that you can use for future import compilations and does not implement the guaranteed timing flow.
|import_compile.tcl||Tcl script for the SDK-user compilation flow (that is, import revision compilation).|
Intel® Quartus® Prime Settings File that collects all the required .ip files in a unique location.
During flat and base revision compilations, the board.qsys Platform Designer file is added to the opencl_bsp_ip.qsf file.
|quartus.ini||Contains any special Intel® Quartus® Prime software options that you need when compiling OpenCL kernels for the a10soc Reference Platform.|
|top.qpf||Intel® Quartus® Prime Project File for the OpenCL hardware system.|
|top.qsf||Intel® Quartus® Prime Settings File for the SDK-user compilation flow.|
|top.sdc||Synopsys® Design Constraints File that contains board-specific timing constraints.|
|top.v||Top-level Verilog Design File for the OpenCL hardware system.|
|ip/freeze_wrapper.v||Verilog Design File that implements the freeze logic placed at outputs of the PR region.|
Directory containing the .ip files that the Intel® Quartus® Prime Pro Edition software needs to parameterize the acl_kernel_interface_soc_pr component.
You must provide both the acl_kernel_interface_soc_pr.qsys file and the corresponding .ip files in this directory to the Intel® Quartus® Prime Pro Edition software.
Directory containing the .ip files that the Intel® Quartus® Prime Pro Edition software needs to parameterize the board system.
You must provide both the board.qsys file and the corresponding .ip files in this directory to the Intel® Quartus® Prime Pro Edition software.
Directory containing the .ip files that the Intel® Quartus® Prime Pro Edition software needs to parameterize the DMA_system component in a10soc_2ddr board variant.
You must provide both the DMA_system.qsys file and the corresponding .ip files in this directory to the Intel® Quartus® Prime Pro Edition software.
Directory containing the .ip files that the Intel® Quartus® Prime Pro Edition software needs to parameterize the dual_port_splitter component.
You must provide both the dual_port_splitter.qsys file and the corresponding .ip files in this directory to the Intel® Quartus® Prime Pro Edition software.
|ip/irq_controller/<file_name>||IP that receives interrupts from the OpenCL kernel system and DMA_system, and sends single IRQ to the host.|
|ip/mem_splitter_port/<file_name>||IP that splits requests across multiple channels on burst word boundary.|
|scripts/base_write_sdc.tcl||Tcl script that the base revision compilation uses to generate the base.sdc file that contains all the constraints collected in the base revision compilation. The Intel® Quartus® Prime Pro Edition software uses the base.sdc file when compiling the import (top) revision.|
|scripts/create_fpga_bin_pr.tcl||Tcl script that generates the fpga.bin file. The fpga.bin file contains all the necessary files for configuring the FPGA.|
|scripts/post_flow_pr.tcl||Tcl script that implements the guaranteed timing closure flow.|
|scripts/pre_flow_pr.tcl||Tcl script that executes before the invocation of the Intel® Quartus® Prime software compilation. Running the script generates the Platform Designer HDL for board.qsys and kernel_mem.qsys. It also creates a unique ID for the PR base revision (that is, static region). This unique ID is stored in the pr_base.id file.|
|scripts/qar_ip_files.tcl||Tcl script that packages up base.qdb, pr_base.id and base.sdc during base revision compile.|
|scripts/regenerate_cache.tcl||Tcl script that regenerates the BAK cache file in your temporary directory.|
Did you find the information on this page useful?