Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide

ID 683788
Date 10/08/2019
Public
Document Table of Contents

1.5. Changes in Intel Arria 10 SoC Development Kit Reference Platform from 17.0 to 17.1

Following is a list of what has changed in a10soc Reference Platform from 17.0 to 17.1 release:
Table 3.  Changes in a10soc Reference Platform from 17.0 to 17.1
File Change
import_compiles.tcl Updated the file for incremental and fast compile features.
board_spec.xml Updated the version from 17.0 to 17.1.
quartus.ini Added qhd_skip_pr_revision_type_check=on INI to the file.
scripts/post_flow_pr.tcl Updated the file to:
  • Enable the fast compile feature.
  • Remove manual call to quartus_cpf for creating PR programming file since it now done automatically in the flow.
scripts/create_fpga_bin_pr.tcl Added the Quartus version as part of fpga.bin.
scripts/qar_ip_files.tcl Updated the file to include:
  • Changes required for renaming .qsys files.
  • Changes required for moving other tcl scripts into Intel® FPGA SDK for OpenCL™ .
scripts/regenerate_cache.tcl Updated the file to include changes required to move bak_flow.tcl into Intel® FPGA SDK for OpenCL™ .
scripts/bak_flow.tcl Moved the file into Intel® FPGA SDK for OpenCL™ .
scripts/helpers.tcl Moved the file into Intel® FPGA SDK for OpenCL™ .
board.qsys
  • Moved the base address of PR IP from 0xcfb0 to 0xcf00.
  • Increased the ACL_VERSIONID to 0xA0C7C1E2 due to the PR IP address change.
  • Synced all IPs.
hw_mmd_constants.h Increased the ACL_VERSIONID to 0xA0C7C1E2 due to the PR IP address change.
base.qar Updated the file with ACDS 17.1 static region.

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