Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide

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ID 683788
Date 10/08/2019
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide 2. Developing an Intel Arria 10 SoC Custom Platform 3. Building the Software and SD Card Image for the Intel® Arria® 10 SoC Development Kit Reference Platform 4. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide Archives 5. Document Revision History for Intel® FPGA SDK for OpenCL™ : Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide
1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide x
1.1. Intel Arria 10 SoC Development Kit Reference Platform: Prerequisites 1.2. Features of the Intel Arria 10 SoC Development Kit Reference Platform 1.3. Intel Arria 10 SoC Development Kit Reference Platform Board Variants 1.4. Contents of the Intel Arria 10 SoC Development Kit Reference Platform 1.5. Changes in Intel Arria 10 SoC Development Kit Reference Platform from 17.0 to 17.1 1.6. Changes in Intel Arria 10 SoC Development Kit Reference Platform from 17.1.2 to 18.0
2. Developing an Intel Arria 10 SoC Custom Platform x
2.1. Initializing an Intel Arria 10 SoC Custom Platform 2.2. Modifying Your Intel Arria 10 SoC Custom Platform 2.3. Integrating Your Intel Arria 10 SoC Custom Platform with the Intel® FPGA SDK for OpenCL™ 2.4. Changing the Device Part Number 2.5. Modifying the Kernel PLL Reference Clock 2.6. Modifying the Hard Processor System 2.7. Guaranteeing Timing Closure in the Intel Arria 10 SoC Custom Platform 2.8. Generating the base.qar Post-Fit Netlist for Your Intel Arria 10 SoC FPGA Custom Platform
3. Building the Software and SD Card Image for the Intel® Arria® 10 SoC Development Kit Reference Platform x
3.1. Compiling the Device Tree Blob 3.2. Compiling the Linux Kernel for the Intel Arria 10 SoC Development Kit 3.3. Compiling the OpenCL Linux Kernel Driver 3.4. Generating Full-Chip Programming File for SD Card Image 3.5. Building the SD Card Image 3.6. Known Issues
3.5. Building the SD Card Image x
3.5.1. Layout of the OpenCL Micro SD Card 3.5.2. Creating the SD Card Image 3.5.3. Guidelines on Imaging the Micro SD Card
3.5.2. Creating the SD Card Image x
3.5.2.1. Creating Partition 1 of the SD Card Image 3.5.2.2. Creating Partition 2 of the SD Card Image 3.5.2.3. Creating Partition 3 of the SD Card Image
1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide
2. Developing an Intel Arria 10 SoC Custom Platform
3. Building the Software and SD Card Image for the Intel® Arria® 10 SoC Development Kit Reference Platform
4. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide Archives
5. Document Revision History for Intel® FPGA SDK for OpenCL™ : Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide

1.5. Changes in Intel Arria 10 SoC Development Kit Reference Platform from 17.0 to 17.1

Following is a list of what has changed in a10soc Reference Platform from 17.0 to 17.1 release:
Table 3.  Changes in a10soc Reference Platform from 17.0 to 17.1
File Change
import_compiles.tcl Updated the file for incremental and fast compile features.
board_spec.xml Updated the version from 17.0 to 17.1.
quartus.ini Added qhd_skip_pr_revision_type_check=on INI to the file.
scripts/post_flow_pr.tcl Updated the file to:
  • Enable the fast compile feature.
  • Remove manual call to quartus_cpf for creating PR programming file since it now done automatically in the flow.
scripts/create_fpga_bin_pr.tcl Added the Quartus version as part of fpga.bin.
scripts/qar_ip_files.tcl Updated the file to include:
  • Changes required for renaming .qsys files.
  • Changes required for moving other tcl scripts into Intel® FPGA SDK for OpenCL™ .
scripts/regenerate_cache.tcl Updated the file to include changes required to move bak_flow.tcl into Intel® FPGA SDK for OpenCL™ .
scripts/bak_flow.tcl Moved the file into Intel® FPGA SDK for OpenCL™ .
scripts/helpers.tcl Moved the file into Intel® FPGA SDK for OpenCL™ .
board.qsys
  • Moved the base address of PR IP from 0xcfb0 to 0xcf00.
  • Increased the ACL_VERSIONID to 0xA0C7C1E2 due to the PR IP address change.
  • Synced all IPs.
hw_mmd_constants.h Increased the ACL_VERSIONID to 0xA0C7C1E2 due to the PR IP address change.
base.qar Updated the file with ACDS 17.1 static region.
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