Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide

ID 683788
Date 10/08/2019
Public
Document Table of Contents

2.3. Integrating Your Intel Arria 10 SoC Custom Platform with the Intel® FPGA SDK for OpenCL™

After modifying the Intel® Quartus® Prime design files, integrate your Custom Platform with the Intel® FPGA SDK for OpenCL™ .
  1. Update the <your_custom_platform>/hardware/<board_name>/board_spec.xml file. Ensure that there is at least one global memory interface, and all the global memory interfaces correspond to the exported interfaces from the board.qsys Platform Designer System File.
  2. Use the -bsp-flow=flat attribute to compile the flat revision corresponding to <your_custom_platform>/hardware/<board_name>/flat.qsf file without the partitions or Logic Locks.
    Tip: Intel recommends to get a timing clean flat revision compiled before proceeding to the base revision compiles.
    aoc -bsp-flow=flat boardtest.cl -o=bin/boardtest.aocx
  3. Use the -bsp-flow=base attribute to compile the base revision corresponding to <your_custom_platform>/hardware/<board_name>/base.qsf file.
  4. Perform the steps outlined in the INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/tests/README.txt file to compile the INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest/boardtest.cl OpenCL kernel source file.
    The environment variable INTELFPGAOCLSDKROOT points to the location of the Intel® FPGA SDK for OpenCL™ installation.
  5. If compilation fails because of timing failures, fix the errors, or compile INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest.cl with different seeds. To compile the kernel with a different seed, include the -seed=<N> option in the aoc command (for example, aoc -seed=2 boardtest.cl ).

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