Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide

ID 683788
Date 10/08/2019
Public
Document Table of Contents

2.2. Modifying Your Intel Arria 10 SoC Custom Platform

After initializing your Intel Arria 10 SoC Custom Platform, modify the existing Intel® Quartus® Prime design in <your_custom_platform> to fit your design needs.
  1. Instantiate or edit the HPS IP parameters.
  2. Instantiate any controllers required (for example, memory controllers, PR controllers and so on) and I/O channels, if required. You can add the board interface hardware either as Platform Designer components in the board.qsys Platform Designer system or as HDL in the top.v file.
    The board.qsys file and the top.v file are in the <your_custom_platform>/hardware/<board_name> directory.
  3. Modify the <your_custom_platform>/hardware/<board_name>/flat.qsf file to use only the pin-outs and settings for your system.
  4. Update the offset addresses of controllers in the respective header files in <your_custom_platform>/arm32/drivers directory, if you modified any controllers in your design.

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