Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide

ID 683788
Date 10/08/2019
Public
Document Table of Contents

2.6. Modifying the Hard Processor System

The Intel® Arria® 10 SoC Development Kit Reference Platform uses HPS as the host system. You can modify the HPS settings in the <your_custom_platform>/hardware/<board_name>/board.qsys file. Regenerate the uboot bootloader after you change the HPS settings.

In the reference design, the HPS IP was instantiated with FPGA-to-HPS interface width set to "128-bit AXI", F2SDRAM port configuration set to "Port Configuration 3" and F2SDRAM0 and F2SDRAM2 enabled.

This instantiation was done to maximize kernel to HPS memory bandwidth. A custom IP module was instantiated between kernel memory interface and the two SDRAM ports to split kernel memory access across the ports.

Attention: You must regenerate the uboot bootloader after you change any HPS settings. For instructions on regenerating the bootloader, refer the Intel® SoC Embedded Design Suite User Guide .

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