Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide

ID 683788
Date 10/08/2019
Public
Document Table of Contents

2.5. Modifying the Kernel PLL Reference Clock

The Intel Arria® 10 SoC Development Kit Reference Platform uses an external 100 MHz clock as a reference for the I/O PLL. The I/O PLL relies on this reference clock to generate the internal kernel_clk clock, and the kernel_clk2x clock that runs at twice the frequency of kernel_clk. When porting the a10soc Reference Platform to your own board using a different reference clock, update the board.qsys and top.sdc files with the new reference clock speed.
  1. In the <your_custom_platform>/hardware/<board_name>/board.qsys file, update the REF_CLK_RATE parameter value on the kernel_clk_gen IP module.
  2. In the <your_custom_platform>/hardware/<board_name>/top.sdc file, update the create_clock assignment for kernel_pll_refclk.
After you update the board.qsys and the top.sdc files, the post_flow_pr.tcl script will automatically determine the I/O PLL reference frequency and compute the correct PLL settings.

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