Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 SoC Development Kit Reference Platform Porting Guide

ID 683788
Date 10/08/2019
Public
Document Table of Contents

2.8. Generating the base.qar Post-Fit Netlist for Your Intel Arria 10 SoC FPGA Custom Platform

To implement a top compilation flow, you must generate a base.qar Intel® Quartus® Prime Archive File for your Intel® Arria® 10 SoC Custom Platform.

The steps below represent a general procedure for regenerating the base.qar file:

  1. Port the system design and the flat.qsf file to your computing card.
  2. Ensure that the AOCL_BOARD_PACKAGE_ROOT environment variable points to your Custom Platform.
  3. Compile the INTELFPGAOCLSDKROOT/board/custom_platform_ toolkit/tests/boardtest/boardtest.cl kernel source file using the base revision. Fix any timing failures and recompile the kernel until timing is clean.
    Attention: Add the -bsp-flow=base argument to the aoc command to generate a base.qar file during the kernel compilation.
  4. Copy the generated base.qar file (which contains the base.qdb and pr_base.id files) into your Custom Platform.
  5. Using the default compilation flow, test the base.qdb file across several OpenCL™ design examples and confirm that the following criteria are satisfied:
    • All compilations close timing.
    • The OpenCL design examples achieve satisfactory Fmax.
    • The OpenCL design examples function on the accelerator board.

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