188.8.131.52. Programming CvP Images
After loading the periphery image, the Intel Agilex® 7 FPGA is triggered to reconfigure from AS to load it. The link should reach the expected data rate and link width. You can confirm the PCIe* link status using the RW Utilities. Follow these steps to program and test the CvP functionality:
- Plug the Intel Agilex® 7 FPGA PCIe* card into the PCI Express slot of the DUT PC and power it ON.
- Open the Intel® Quartus® Prime Tools menu and select Programmer.
- Click Auto Detect to verify that the Intel® FPGA Download Cable recognizes the Intel Agilex® 7 FPGA.
- Follow these steps to program the periphery image:
- Select Intel Agilex® 7 device, and then right click None under File column and select Change File.
- Navigate to .periph.jic file and click Open.
- Under Program/Configure column, select the respective devices.
- Click Start to program the periphery image into flash.
- After the .periph.jic is programmed, the FPGA must be powered cycle to allow the new peripheral image to load from the on-board flash into the FPGA. To force the DUT PC to re-enumerate the link with the new image, power cycle the DUT PC and the Intel Agilex® 7 FPGA PCIe* card.
- You can use RW Utilities or another system software driver to verify the link status. You can also confirm expected link speed and width.
- Follow these steps to program the core image via PCIe link:
- Copy the .core.rbf file into /lib/firmware
- In the /lib/firmware directory, run the following command to use the FPGA manager to configure the core image.
- Run: su to get root access.
echo <filename>.core.rbf > /sys/kernel/debug/fpga_manager/fpga0/firmware_name
- You can see your core image running on the Intel Agilex® 7 FPGA PCIe* card. Alternatively, print out the kernel message using the dmesg to ensure the CvP is completed successfully.
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